Register renaming is a critical component and has long been a challenge in microprocessor design. There are two kinds of condition code instructions that require implementation of register renaming, instructions that set condition code bits and instructions that test the condition code bits. For an out of order execution pipeline device, the challenge is to keep track of the dependency between the two kinds of condition code instructions. In conventional microprocessors, a (CAM) structure is used to check such dependencies. However, when the size of the active condition code instruction list increases, the CAM structure becomes proportionately bigger and timing becomes constrained.